An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, capacitors, and resistors. Commonly known as a “chip” or a “package”, an integrated circuit is generally encased in rigid plastic, forming a “package”. The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement. Often, many such packages are electrically coupled so that the chips therein form an electronic circuit to perform certain functions.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A layout includes shapes that the designer selects and positions to achieve a design objective. The objective is to have the shape—the target shape—appear on the wafer as designed. However, the shapes may not appear exactly as designed when manufactured on the wafer through photolithography. For example, a rectangular shape with sharp corners may appear as a rectangular shape with rounded corners on the wafer.
Once a design layout, also referred to simply as a layout, has been finalized for an IC, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacture, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components of the IC. This process is known as photolithography.
A manufacturing mask is a mask usable for successfully manufacturing or printing the contents of the mask onto wafer. During the photolithographic printing process, radiation is focused through the mask and at certain desired intensity of the radiation. This intensity of the radiation is commonly referred to as “dose”. The focus and the dosing of the radiation is controlled to achieve the desired shape and electrical characteristics on the wafer.
A Field Effect Transistor (FET) is a semiconductor device that has controls the electrical conductivity between a source of electric current (source) and a destination of the electrical current (drain). The FET uses a semiconductor structure called a “gate” to create an electric field, which controls the free charged carriers and consequently the electrical conductivity of a channel between the source and the drain. The channel is a charge carrier pathway constructed using a semiconductor material.
Many semiconductor devices are planar, i.e., where the semiconductor structures are fabricated on one plane. A non-planar device is a three-dimensional (3D) device where some of the structures are formed above or below a given plane of fabrication.
A fin-Field Effect Transistor (finFET) is a non-planar device in which a source and a drain are connected using a fin-shaped conducting channel (fin). Accordingly, the direction of electrical current is along the lateral length of the fin running from the source to the drain is referred to herein as a lateral running direction of the current.
The illustrative embodiments recognize that the present methods and techniques for fabricating electrical contacts for p-type field effect transistor (pFET)device and an n-type field effect transistor (nFET) device on a common substrate suffer from several problems. For example, in conventional contact formation use of a reactive-ion etching (RIE) process during fabrication may cause contact damage from plasma and leave polymer residue at the bottom of the contact trench of the semiconductor. In addition, traces of silicon nitride (SiN) may remain in the trench. As a result of the poor surface condition of the trench, contacts formed in this manner may produce an undesirable increase in contact resistance at the metal-semiconductor (M-S) junction. In addition, gouging of the source-drain (SD) epitaxial layer may occur encroaching upon the fin structure of the semiconductor.
The illustrative embodiments recognize that it is difficult to fabricate contacts for a p-type field effect transistor (pFET) device and an n-type field effect transistor (nFET) device on the same substrate while maintaining a low contact resistance between the metallic contacts and semiconductor material of the FET body for both the pFET device and the nFET device. Therefore, a method for fabricating contacts for a p-type field effect transistor (pFET) device and an n-type field effect transistor (nFET) device on a common substrate while maintaining a low contact resistance between the contacts and semiconductor material of the FET body for both the pFET device and the nFET device would be useful.